Modem integrated circuits contain millions of devices to achieve complex functions. The electrical connection between the devices in such semiconductor circuits is provided by fine wires of conductive metals known as interconnects. As integrated circuit chips have become larger and more complex the requirements placed on the interconnect systems have also increased. As a result, interconnects have evolved from a single layer of aluminum to several levels of metal interconnects extending in channels formed horizontally and vertically in the body of the chip. In the multilevel metallization scheme insulating interlayer dielectric layers separate the silicon or local interconnect lines from each other. The linkage from one layer of interconnect to another is provided by vias, which are opened in the interlayer dielectric layers and then filled by metal.
Because of several advantages, copper has recently become the preferred metal of interconnect applications, replacing aluminum and its alloys. The preferred method of forming copper interconnects is the damascene process. In the damascene method, copper is generally deposited using electroplating processes onto a dielectric diffusion layer previously deposited into vias and trenches that are previously etched in the interlayer dielectric. Chemical mechanical planarization (CMP) is then used to planarize the deposited copper layer, barrier layer and even the interlayer dielectric following the copper deposition.
FIG. 1 schematically shows exemplary arrays of features that are formed in the dielectric layer 10 on an exemplary semiconductor substrate. These features need to be filled by electroplated copper to form copper interconnects. As an example, a first array 11 of features may be sub-micron size trenches with widths in the range of 0.05–0.5 microns. A second array 12 of features may be trenches with widths in the range of 0.5–2 microns. A third array 13 of features may be trenches with widths in the range of 2–5 microns. Before electroplating, barrier and seed layers are deposited over the whole surface and into the arrays 11, 12 and 13 of the substrate as is well known in the field. Such layers will not be shown in FIG. 1 for clarification purpose.
Electroplating solutions typically contain organic additives such as accelerators, suppressors and levelers in their formulations. Commonly used electrolytes are copper sulfate solutions supplied by companies such as Enthone and Shipley. The additives in the plating solutions help provide smooth deposits and bottom up growth in small features.
FIG. 2 shows the typical evolution of copper thickness profiles A, B, C and D over the substrate surface depicted in FIG. 1, when electrodeposition is carried out from electrolytes containing accelerator and suppressor species. As the plating is initiated by applying a cathodic voltage to the wafer with respect to an anode, copper first starts to deposit conformally. Then bottom-up growth is initiated and the first array 11 of the smallest features is quickly filled, for example at time T1. Thickness profile at time T1 is represented by profile A. As can be seen from FIG. 2, at time T1 the larger features are still not fully filled with copper. Deposition is then continued to fill the larger features. Thickness profile B represents the copper profile at a time T2 when the second array 12 of features is completely filled by copper. As the second array 12 is filled however, the accelerator species that are responsible for bottom-up fill of the features cause a bump or overfill 20 over the first array 11. The reason for this phenomenon is believed to be the high accelerator concentration that stays over the first array 11, even after the fill is complete. Similarly, thickness profile C shows that as the third array is completely filled another bump is formed, this time over the second array 12. If plating is continued, eventually a third bump may also be formed over the third array 13 as shown in profile D.
Non-flat profile depicted as profile D in FIG. 2 presents challenges for the CMP process. During CMP, surface of dense arrays that are overfilled need to be cleared off copper to avoid shorting between the features. This requires over-polishing, which in turn causes dishing and erosion defects as well known in the art. It should be noted that the bumps may have a copper thickness of more than 2000 Å (for example 2000–6000 Å) compared to the region of the wafer where there are isolated large features. A flat copper thickness profile is therefore preferred for the best results after the CMP step of the interconnect fabrication process. In some prior art applications, levelers may be used to minimize bump formation over the dense arrays. However, levelers cannot completely eliminate the bump formation problems.
Defect-free filling of the small features is another requirement for interconnect fabrication. Copper deposited into the vias and trenches needs to be free of voids, seams and other defects to avoid high resistance and reliability problems. Plating solutions with bottom-up filling capability are formulated to minimize such defects. In addition to the formulation of the bath, plating waveform which is the voltage/current applied to the wafer is also an important factor in minimizing or eliminating fill-related defects. For example, in the prior art, applying reverse pulses (anodic pulses) to the wafer during early stages of the plating period is shown to improve filling properties of the smallest features. Example of such prior art processes may be seen in U.S. Pat. Nos. 5,972,192, 6,297,155 and 6,303,014. Generally, reverse pulses used in the prior art are applied in short time durations in millisecond level. Further, prior art reverse pulses are either applied during the gap file period or throughout the plating period.